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this is information on a product in full production. april 2014 docid16936 rev 5 1/13 13 esdalc5-1bm2, ESDALC5-1BT2 single-line low capacitance transil?, transient surge voltage suppressor (tvs) for esd protection datasheet ? production data features ? single-line low capacitance transil diode ? bidirectional esd protection ? breakdown voltage v br = 5.8 v min. ? low diode capacitance (26 pf typ at 0 v) ? low leakage current < 60 na at 5 v ? very small pcb area: 0.6 mm2 benefits ? high esd protection level ? high integration ? suitable for high density boards ? lead-free packages ? ecopack ? 2 compliant components complies with the following standards: ? iec 61000-4-2 (exceeds level 4) ? 30 kv (air discharge) ? 30 kv (contact discharge) ? mil std 883g - method 3015-7: class 3 ? human body model applications where transient overvoltage protection in esd sensitive equipment is required, such as: ? computers ? printers ? communication systems ? cellular phone handsets and accessories ? video equipment description the esdalc5-1bm2 and ESDALC5-1BT2 are bidirectional single-line tvs diodes designed to protect data lines or other i/o ports against esd transients. these devices are ideal for applications where both reduced line capacitance and board space saving are required. figure 1. functional diagram tm : transil is a trademark of stmicroelectronics sod882 esdalc5-1bm2 sod882t ESDALC5-1BT2 i/o1 i/o2 www.st.com
characteristics esdalc5-1bm2, ESDALC5-1BT2 2/13 docid16936 rev 5 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge 30 30 kv p pp peak pulse power dissipation (8/20 s) t j initial = t amb 150 w i pp peak pulse current (8/20 s) 9 a t j operating junction temperature range -55 to +150 c t stg storage temperature range -65 to +150 c t l maximum lead temperature for soldering during 10 s 260 c table 2. electrical characteristics (values, t amb = 25 c) symbol test condition min. typ. max. unit v br from i/o1 to i/o2, i r = 1 ma 11 13 17 v from i/o2 to i/o1, i r = 1 ma 5.8 8 11 i rm v rm = 5 v 60 na r d dynamic resistance, pulse width 100 ns from i/o1 to i/o2 from i/o2 to i/o1 0.25 0.23 ? c line f = 1 mhz, v r = 0 v 26 30 pf v cl 8 kv contact discharge after 30 ns iec 61000 4-2 from i/o1 to i/o2 from i/o2 to i/o1 17.5 12.5 v symbol parameter v = breakdown voltage br v = clamping voltage cl i = leakage current at v rm rm v = stand-off voltage rm i = peak pulse current pp i = breakdown current r r = dynamic resistance d v = triggering voltage trig c = input capacitance per line line v cl v br v rm i r i pp v i v trig i rm
docid16936 rev 5 3/13 esdalc5-1bm2, ESDALC5-1BT2 characteristics figure 3. peak pulse power dissipation versus initial junction temperature (maximum values) figure 4. leakage current versus junction temperature (typical values) p pp (w) 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 8/20s t j (c) i r (na) 0,01 0,1 1 10 100 1000 25 50 75 100 125 150 v r = v rm = 5 v f romi/o1 to i/o2 t j (c) figure 5. leakage current versus junction temperature (typical values) figure 6. peak pulse power versus exponential pulse duration (maximum values) i r (na) 0,01 0,1 1 10 100 1000 25 50 75 100 125 150 v r = v rm = 5 v f romi/o2 to i/o1 t j (c) p pp (w) 1 10 100 1000 10000 1 10 100 1000 tp(s) figure 7. clamping voltage versus peak pulse current (typical values) figure 8. clamping voltage versus peak pulse current (typical values) 0,1 1 10 12 13 14 15 16 17 18 19 20 21 22 23 i pp (a) 8/20s t j initial = 25 c from i/o1 to i/o2 v cl (v) i pp (a) 0,1 1 10 7 8 9 10111213141516 8/20s t j initial = 25 c from i/o2 to i/o1 v cl (v)
characteristics esdalc5-1bm2, ESDALC5-1BT2 4/13 docid16936 rev 5 figure 9. junction capacitance versus reverse applied voltage (typical values from i/o1 to i/o2) figure 10. junction capacitance versus reverse applied voltage (typical values from i/o2 to i/o1) c(pf) 0 5 10 15 20 25 30 35 012345 t j = 25-c f = 1mhz vosc = 30mv from i/o1 to i/o2 v r (v) 0 5 10 15 20 25 30 35 012345 t j = 25-c f = 1mhz vosc = 30mv from i/o2 to i/o1 c(pf) v r (v) figure 11. esd response to iec 61000-4-2 (+8 kv air discharge) figure 12. esd response to iec 61000-4-2 (-8 kv air discharge) 10 v/div 40 v 16 v 16 v 12 v 20 ns/div v : esd peak voltage pp v :clamping voltage @ 30 ns cl v :clamping voltage @ 60 ns cl v :clamping voltage @ 100 ns cl 1 1 1 2 2 2 2 3 3 4 4 4 4 3 3 10 v/div -35 v -11 v -11 v -1 v 20 ns/div v : esd peak voltage pp v :clamping voltage @ 30 ns cl v :clamping voltage @ 60 ns cl v :clamping voltage @ 100 ns cl 1 1 1 1 2 2 2 2 3 3 4 4 4 4 3 3 figure 13. s21 attenuation measurement result figure 14. tlp measurement 100k 1m 10m 100m 1g - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 db f(hz) i pp (a) 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 from i/o2 to i/o1 from i/o1to i/o2 v cl (v)
docid16936 rev 5 5/13 esdalc5-1bm2, ESDALC5-1BT2 package information 2 package information ? epoxy meets ul94, v0 ? lead-free packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 15. sod882 dimension definitions table 3. sod882 dimension values ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.40 0.47 0.50 0.016 0.019 0.020 a1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 d 0.55 0.60 0.65 0.022 0.024 0.026 e 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 l1 0.20 0.25 0.30 0.008 0.010 0.012 l2 0.20 0.25 0.30 0.008 0.010 0.012 pin # 1 id e d a1 a l1 e l2 b2 b1
package information esdalc5-1bm2, ESDALC5-1BT2 6/13 docid16936 rev 5 note: product marking may be rotated by multiples of 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only i/o1 mark is to be used for this purpose. figure 18. sod882 tape and reel specifications figure 16. sod882 footprint in mm (inches) figure 17. sod882 marking 0.55 (0.022) 0.40 (0.016) 0.55 (0.022) 0.50 (0.020) i/o1 i/o2 g user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 + 0.3 /-0.1 2.0 0.10 1.75 0.1 3.5 - 0.05 ? 1.50 0.10 0.68 0.05 0.20 0.05 1.10 0.05 x x x x x x x 0.66 0.05 bar indicates pin 1
docid16936 rev 5 7/13 esdalc5-1bm2, ESDALC5-1BT2 package information figure 19. sod882t dimension definitions table 4. sod882t dimension values ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.30 0.40 0.012 0.016 a1 0.00 0.05 0.000 0.002 b1 0.45 0.50 0.55 0.018 0.020 0.022 b2 0.45 0.50 0.55 0.018 0.020 0.022 d 0.55 0.60 0.65 0.022 0.024 0.026 e 0.95 1.00 1.05 0.037 0.039 0.041 e 0.60 0.65 0.70 0.024 0.026 0.028 l1 0.20 0.25 0.30 0.008 0.010 0.012 l2 0.20 0.25 0.30 0.008 0.010 0.012 figure 20. sod882t footprint in mm (inches) figure 21. sod882t marking pin # 1 id e d a1 a l1 e l2 b2 b1 0.50 (0.020) 0.55 (0.022) 0.40 (0.016) 0.55 (0.022) i/o1 i/o2 h
package information esdalc5-1bm2, ESDALC5-1BT2 8/13 docid16936 rev 5 note: product marking may be rotated by multiples of 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only i/o1 mark is to be used for this purpose. figure 22. sod882t tape and reel specifications user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 0.1 2.0 0.10 1.75 0.1 3.5 - 0.05 ? 1.50 0.10 0.70 0.05 0.20 0.05 1.15 0.05 x x x x x x x 0.47 0.05 bar indicates pin 1
docid16936 rev 5 9/13 esdalc5-1bm2, ESDALC5-1BT2 recommendation on pcb assembly 3 recommendation on pcb assembly 3.1 stencil opening design 1. general recommendation on stencil opening design a) stencil opening dimensions: l (length), w (width), t (thickness). figure 23. stencil opening dimensions b) general design rule stencil thickness (t) = 75 ~ 125 m 2. reference design a) stencil opening thickness: 100 m b) stencil opening for central exposed pad: opening to footprint ratio is 50%. c) stencil opening for leads: opening to footprint ratio is 90%. figure 24. recommended stencil window position in mm (inches) l t w aspect ratio w t ----- 1,5 = aspect area lw 2t l w + () --------------------------- - 0,66 = lead footprint on pcb stencil window opening 0.55 (0.022) 0.50 (0.020) 0.40 (0.016) 0.522 (0.021) 0.474 (0.019) 0.014 (0.00055) 0.014 (0.00055) 0.013 (0.00051) 0.013 (0.00051)
recommendation on pcb assembly esdalc5-1bm2, ESDALC5-1BT2 10/13 docid16936 rev 5 3.2 solder paste 1. halide-free flux qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste is recommended. 3. offers a high tack force to resist component movement during high speed. 4. solder paste with fine particles: powder particle size is 20-45 m. 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead rec ognition capabilities of th e placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks a nd open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
docid16936 rev 5 11/13 esdalc5-1bm2, ESDALC5-1BT2 recommendation on pcb assembly 3.5 reflow profile figure 25. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
ordering information esdalc5-1bm2, ESDALC5-1BT2 12/13 docid16936 rev 5 4 ordering information figure 26. ordering information scheme 5 revision history table 5. ordering information order code marking (1) 1. the marking can be rotated by multiples of 90 to differentiate assembly location package weight base qty delivery mode esdalc5-1bm2 g sod882 0.93 mg 12000 tape and reel ESDALC5-1BT2 h sod882t 0.82 mg 12000 tape and reel esda lc 5 - 1 b x2 esd array low capacitance package m2 = sod882 t2 = thin sod882 breakdown voltage number of lines directional 5 = 5 volts min b = bi-directional table 6. document revision history date revision changes 02-feb-2010 1 initial release. 06-jun-2012 2 updated figure 11 , figure 12 , figure 15 , figure 19 , table 3 , and table 4 . updated note in page 7, 8 and 13. updated i rm in table 2 . 05-mar-2013 3 clamping voltage at 30 ns added in table 2 . 09-jan-2014 4 updated table 1 , table 2 , table 5 , figure 2 , figure 3 , figure 4 , figure 5 , figure 6 , figure 7 , figure 8 , figure 9 , figure 10 , figure 11 , figure 12 , figure 16 , figure 17 , figure 20 , figure 21 and figure 24 . added figure 14 . 02-apr-2014 5 updated figure 4 and figure 5 .
docid16936 rev 5 13/13 esdalc5-1bm2, ESDALC5-1BT2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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